A Capacitor-Less LDO Regulator Compensated by Adaptive Zero for Zero-Load Stability Enhancement

A flipped voltage follower (FVF)-based capacitor-less low-dropout (LDO) regulator is presented that features a fast transient response. The adaptive zero compensation is proposed to solve the full-load-range stability issue associated with the FVF LDO regulator. The presented FVF LDO regulator has been implemented in a 0.18 μm CMOS process with an active area of 0.026 mm
²
. The simulated loop phase margin exceeds 45° for the entire load range of 0-40 mA. The minimum power supply rejection of 56 dB at 1 MHz has been measured at the maximum load current of 40 mA. The measured transient response time is 0.48 ns over the load current range with a dynamic quiescent current of 36 to 76 μA, which results in a figure of merit among the best reported in recent publications.