A Data-Distribution Aware Approximate Multiplier Design Based on FPGA

The approximate multiplier (AM) serves as a computing unit that saves hardware resources and power consumption at the expense of computational accuracy. This paper proposes a data-distribution aware approximate multiplier (DDAM) design for FPGAs. We build a numerical optimization model for automatic design space exploration of DDAM. Furthermore, we propose a weight-based iterative algorithm (WIA) to accelerate the solution of the optimization model. Experimental results demonstrate that WIA significantly reduces DDAM design exploration time to approximately 0.05% of a generic search method. The generated DDAM reduces the average error by about 43% compared to approximate multipliers with uniform data distribution. Furthermore, in an 8 × 8 multiplication scenario, DDAM reduces LUT utilization by 48% compared to the Xilinx’s accurate multiplier IP core. Compared to existing FPGA-based AMs, DDAM achieves the best balance between accuracy and area.