An 800 kS/s 1.83 fJ/conv. 12b ADC via Voltage Successive Approximation and Gated Cyclic Vernier Time Digitization

A 12b analog-to-digital converter (ADC) consisting of an 8b successive approximation register (SAR) ADC, a voltage-to-time converter (VTC), and a gated cyclic Vernier time-to-digital converter (TDC) is presented. A number of design techniques including a sub-threshold delay-locked loop (DLL) with pulsed outputs to generate the clock signals of the ADC, a power/area-efficient technique to eliminate the kickback-induced errors of the comparator, a gated cyclic Vernier TDC to eliminate resolution loss at both input injection and catch, a self-resetting arbiter, and a power/area-efficient synchronous SAR are proposed. The ADC is designed in a TSMC 130 nm CMOS technology with a reduced supply voltage of 0.8 V. The simulation results of the ADC with a 7.42 kHz 400 ∼ 800 V differential sinusoidal input voltage show that at 800 kS/s, the ADC offers 59.32 dB SNDR and 9.56 ENOB while consuming 3.44 µW, yielding 1.83 fJ/conv. FOM.