Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor

This paper presents the design and analysis of a family of voltage reference generators (VRGs) based on the stacking of a current-source transistor M
I
and a resistive-load transistor M
R
, i.e., stacking of M
I,R
(SMIR) in standard CMOS technology for sub-1V and sub-nW operation. Design guidelines are provided to obtain the reference voltage for various temperature characteristics, namely proportional to absolute temperature (PTAT), complementary to absolute temperature (CTAT), and constant with temperature (CWT), by appropriately sizing the two transistors as current source and load respectively. The proposed 6 such SMIR VRGs in 65nm consume an average power less than 4pW and occupy an area less than 30µm × 100µm when measured from 20 different samples. All VRGs operate at a minimum supply voltage of 0.4V and achieve an average line regulation better than 0.3%/V. For the CWT VRGs, an average temperature coefficient better than 260.9ppm/°C is achieved from -20°C to 80°C.