The Design of a Low-latency Tensor Decomposition Algorithm and VLSI Architecture

Tensor decomposition has emerged as an essential means for applications with multidimensional signals such as data compression and feature extraction. However, due to the enormous amount of signal processing and storage, it is challenging to design a low-latency tensor decomposition processor with high hardware efficiency. This paper presents a low-latency algorithm and VLSI architecture for a tensor decomposition processor. The designed circuit is implemented based on the FPGA platform. The estimation results demonstrate that the proposed architecture achieves a low-latency performance and high hardware efficiency.