A Multi-Stride Convolution Acceleration Algorithm for CNNs

Hardware acceleration is very important in the proliferation of Deep Neural Network (DNN) technologies. The Single Input Partial Product 2-D (SIPP2D)
¹
convolution-based architecture introduced in [1], [2] implements the convolution operation of convolution-based DNNs efficiently by reading the input pixels once and maximizing their reuse. In this paper, we describe the methodology to extend the DNN accelerator based on SIPP2D-based architectures to incorporate multiple strides. We describe the algorithm for any allowable stride, given any (square) input and kernel sizes. We present an analysis of the frequency of reuse of each input pixel and its complementary pixels for multiple strides and as well as its theoretical performance.