A gm/Id based methodology to estimate OTA requirements in low-pass discrete time Σ∆-ADCs

This paper presents an analytical analysis to estimate the optimal slew rate (SR) and gain bandwidth (GBW) requirements of operational transconductance amplifiers (OTA) in discrete-time sigma-delta modulators (DT-Σ∆M). The proposed g
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/I
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approach takes into account the bias condition of the transistor allowing the designer to easily obtain transistor-level design specifications from system-level requirements. The accuracy of the presented study is verified by post-layout simulations of a DT-Σ∆M. The post-layout simulation results are in agreement with system-level predictions even considering process, voltage, and temperature variations.