A Flexible FPGA-Based Accelerator for Efficient Inference of Multi-Precision CNNs

Multi-precision (MP) convolutional neural networks (CNNs) have exploited quantization techniques to achieve notable computation reductions while maintaining accuracy. However, most existing accelerators lack sufficient support for MP multiplications, hindering their ability to satisfy the diverse precision requirements of different layers in MP CNNs. To address this issue, we propose a flexible FPGA-based accelerator that efficiently processes CNN inference, supporting both symmetric and asymmetric bit-width computation. Specifically, a reconfigurable computing unit called MP-MAC is specially designed for efficient execution of MP computations to maximize computation utilization within a single DSP. Additionally, an optimized computing data arrangement, based on our flexible parallelism scheme, is presented to further enhance the performance of MP CNN deployment. Moreover, an MP performance model is introduced to estimate the transmission and computation latency, providing valuable guidance for efficient hardware design. The proposed accelerator achieves a throughput of up to 660.60 GOPS on Intel Arria 10 SoC FPGA, with 3.77× better DSP efficiency compared to prior work when evaluated on the same network.