A 14-bit 6GS/s DAC Achieving >65dBc SFDR with Bilateral Output Impedance Compensation in 22nm CMOS

A 14-bit 6.0-GS/s current-steering digital-to-analog converter (DAC) is presented in this paper. A bilateral output impedance compensation (BOIC) technique is proposed to suppress DAC nonlinearity induced by cell finite output impedance, which is compact, effective and power-efficient. Compensation networks are implemented by two NMOS transistors with code-dependent gate voltage. Furthermore, the calibration structure is improved to enable DAC cell bidirectional calibration, by designing the calibration DAC with a constant current source load. Simulation results in 22-nm CMOS show that The DAC achieves >65-dBc spurious-free dynamic range (SFDR) over the entire Nyquist bandwidth, with a 1.1V supply and an output swing over 0.9Vpp. The DAC core power consumption is only 37mW, showing its merits over state-of-the-art designs.