A Hyperdimensional Computing Architecture with 4.4x Energy Efficiency in 65nm CMOS

Hyperdimensional computing (HDC), a brain-inspired computing defined on high-dimensional vectors (or hypervectors), has emerged as a promising energy-efficient approach for solving classifications tasks. Current HDC architectures typically rely on binary dense hypervectors with approximately equal number of 1 and 0 elements. While these provide good classification performance, they may suffer from high energy consumption due to high switching activity, especially with hypervectors whose dimensionality is in the thousands. In this work, we explore the use of binary sparse representations, in which most of the elements are 0s, for a highly energy-efficient HDC architecture. We consider a language classification task as a case study, targeting 65nm CMOS process. Our results show a remarkable 4.4x reduction in energy and 3.68% reduction in area at iso-performance as compared to when using dense representations. Furthermore, increasing the sparsity in the architecture leads to increased classification accuracy and energy efficiency.