A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit

This paper proposes a low-power 3.2-GHz 0.3/0.5 V I/O Buffer. By using the proposed Output Buffer with parallel PMOS and NMOS transistors as the pull-up and pull-down networks, the 0.3 V low-voltage signal could be transmitted without the extra NLC (Negative Level Converter) as the gate driver. At the Input Buffer, the source terminal of the NMOS transistor is used as the input terminal, such that the 0.3 V input signal could be received without using low threshold-voltage transistors. Moreover, the Low-Power PVT compensation circuit without various threshold-voltage transistors is proposed to compensate the delay time variation for all PVT corners. The proposed design is implemented with TSMC 16-nm FinFET process. The core area is 38.77 × 67.49 μm
²
. With the PVT compensation, the eye height ratio becomes 93% and 94% for VDDIO at 0.3 V and 0.5 V, respectively. The eye width is improved to 0.85 UI. The delay time variation is reduced by 45.03% in the worst case. The power consumption is 5.338 μW/MHz.