Low-Complexity and High-Throughput Number Theoretic Transform Architecture for Polynomial Multiplication in Homomorphic Encryption

The computationally intensive of polynomial ring multiplication in homomorphic encryption (HE) schemes demand an optimized hardware accelerator design, specifically targeted for edge devices. The state-of-the-art algorithm for calculating polynomial ring multiplication is the Number Theoretic Transform (NTT) which is capable of reducing the number of operations needed from the school book multiplication algorithm. In this work, we propose a novel NTT hardware accelerator design that is suitable for use in implementing a partially homomorphic encryption scheme with a 192-bit level of security. The main novelty presented in this paper is the realization of an area-efficient higher radix NTT and inverse NTT (INTT) accelerator which is achieved via mathematical optimization and a point-based approach to calculating NTT. Compared to previous works with similar throughput per slice metric, the design is able to deliver 5.16× higher throughput for a 2.46× increase in slice count.