A 19 fJ/op, Low-Offset StrongARM Latch Comparator for Low-Power High-Speed Applications

In this paper, a new StrongARM latch comparator design has been proposed for low-power high-speed applications. The proposed design improves the energy consumption and propagation delay when compared to the previous designs in the literature. The proposed design is post-layout simulated in TSMC 65 nm technology node and it achieves a low energy consumption of 19.31 fJ per operation and a low propagation delay of 211 ps. Moreover, the proposed design shows a highly favorable input offset voltage of 0.56 mV and achieves a maximum frequency of 8 GHz. Furthermore, the proposed design reduced the transistor stack that allows it to be used in the low-voltage supply application.