On the Segmentation of Gigasample Rate Current Steering DACs

This paper focuses on the impact of segmentation on the linearity performance of gigasample rate current-steering digital-to-analog converters (DACs). The effect of their output impedance drop and code-dependency occurring at increasingly higher data rates is studied with the purpose of deriving relevant design constraints about the segmentation scheme choice. This analysis is supported by extensive simulation results carried out with special attention to the spurious-free-dynamic-range (SFDR) and third-order-intermodulation-distortion (IM3) metrics. Lastly, a 10-bit 6.4 GS/s DAC designed in a 55-nm BiCMOS technology is presented and discussed in relation to the previously determined scenarios. Besides featuring a 65.9-dBc SFDR at 1 GHz and an IM3 < -68.1 dBc over the Nyquist band, it occupies a silicon area below 0.05 mm
²
.