Towards Cycle-accurate Simulation of xBGAS

High-performance computing (HPC) systems are evolving to address big-data and data-intensive workloads, shifting from monolithic architectures to integrated setups with micro-processors, accelerators, and advanced interconnects. However, this transition introduces complexities, latency challenges, and performance bottlenecks in large-scale parallel applications. To tackle these issues, the Extended Base Global Address Space (xBGAS) project enhances memory addressing through innovations in Instruction Set Architecture (ISA) and microarchitecture. Leveraging RISC-V's extensibility, xBGAS integrates an extended register file and new instructions, enabling efficient global memory access. This paper introduces REV-xBGAS, a cycle-based simulator using the Structural Simulation Toolkit (SST) to model xBGAS-enabled processors. With SST's modularity, REV-xBGAS allows easy configuration of network latencies, bandwidths, and topologies, enabling performance evaluations under varied conditions.