A Sub-Band-Aliasing Architecture for Frequency-Interleaved Analog-to-Digital Converters

The frequency-interleaved analog-to-digital converter (FI-ADC) can effectively improve the performance of sampling systems by expanding bandwidth and sampling rate as the number of channels increases. However, this improvement may come with drawbacks such as complex hardware requirements and potential mirror errors resulting from an imbalance between in-phase and quadrature-phase signals within the system. This article proposes an alternative FI-ADC architecture, referred to as the sub-band-aliasing (SA) ADC. In the proposed architecture, the analog input signal is divided into multiple sub-bands, and a mixer modulates the input signal to alias adjacent sub-bands. Subsequently, the modulated signal is fed into a low-pass filter (LPF) and an ADC, after which each sub-band is recovered via a recursive process involving spectrum calculation and shifting. Moreover, potential errors that may arise in practical applications are analyzed and compensated. The simulation results indicate that the proposed architecture demonstrates practical utility and can achieve comparable performance to traditional FI-ADCs while featuring a simpler architecture and a lower hardware cost. Furthermore, the effectiveness of the proposed architecture is also demonstrated by hardware experiments, in which an FI-ADC with a total bandwidth of 6 GHz has been implemented using four channels, each channel having a bandwidth of only 1.5 GHz.