Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part II: PBTI Aging and Optimization

In Part II of this article, we explore the effect of positive bias temperature instability (PBTI) aging on the retention time distribution. By combining TCAD simulations with experiments, we identified the spatial location and energy-level distribution of pre-existing and generated interface states. According to the defect-based compact leakage model established in Part I, simulations reveal the nonnegligible influence of PBTI aging effects on the retention time distribution. Additionally, the effects of buried-channel-array-transistors (BCATs) device parameters and random dopant fluctuation (RDF) on static leakage have been incorporated into the compact model, aiming to optimize the time-zero retention time of weak cells. Investigations focused on several key device parameters in the storage contact (SC) and wordline (WL) overlap region suggest that decreasing the work function (WF) of the top gate is a beneficial strategy. However, optimizing this key parameter will increase the degradation rate of the retention time of weak cells due to the PBTI-induced aging effect. Therefore, when designing aging-aware BCAT devices, tradeoffs need to be made between time-zero retention time, long-term retention time, and read/write performance.