Hardware Implementation of the Multiplier Using Argument Bit Grouping

The paper considers an approach to the construction of multipliers based on the combination of Vedic principles of multiplication and classical algorithm with summation of partial products using matrix architecture. The paper shows the algorithm realized by the multiplier, presents a variant of implementation of the multiplier with two-bit groupings of argument bits, estimates hardware costs and time characteristics of the obtained combinational and pipeline multipliers based on FPGA of Cyclone III family of IntelFPGA company.