Self-Timed Counter Synthesis

Self-timed (ST) circuits have higher reliability in comparison with synchronous counterparts and can serve as a promising circuitry basis for microelectronic control unit implementations for robotic complexes and production systems. However, designing ST circuits is more labor-intensive and non-trivial because of the need to adhere to strict signal generation discipline and build an additional indication subcircuit. The synthesis of combinational ST circuits is quite simply formalized by means of dualizing the logical function system obtained by a logic synthesizer and adding an indication subcircuit. However, when synthesizing ST units with memory, including ST counters, this approach leads to excessive hardware redundancy and, as a consequence, to the resulting solution's low level of performance and soft error tolerance. The article analyzes the circuitry basis for the optimal multi-bit ST counter implementation and proposes a method for synthesizing ST counters based on parameterized templates of the ST counter body and its environment, ensuring self-timed implementation, its full functional compliance with the original description, and close to optimal consumer characteristics.