A Dynamic Offset Reduction Technique to Mitigate the Effect of Threshold Mismatch in Energy Efficient Comparators

This work proposes an energy-efficient offset reduction technique for dynamic comparators. An additional capacitor and four transistors are used to minimize the effect of threshold mismatch by dynamically sampling the common mode and differential signals. The proposed technique reduces the offset by three times compared to the conventional design. Both the conventional and proposed comparators are designed and fabricated in AMS 350 nm CMOS process with a 3.3 V power supply. It occupies an area of
$53.5~\mu $
m
$\times 39.8~\mu $
m. The performance of the comparator is verified over silicon and measurement results are reported in this paper. The worst case comparator offset observed is 2.6 mV at 1.5 V input which increases to 5 mV at 3 V input voltage. The offset is also measured for different die samples and die-to-die variations corresponding to five samples are reported. The maximum error standard deviation observed for different die samples is 0.4 mV.