An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth

This article presents an intrinsically linear continuous-time (CT) zoom analog-to-digital converter (ADC) architecture that uses a coarse first-order CT delta-sigma modulator ( $\Delta \Sigma $ M) followed by a fine third-order CT- $\Delta \Sigma $ M. The 1.5-bit output of the coarse CT- $\Delta \Sigma $ M is filtered by an 8-tap finite impulse response (FIR) filter, and then, a current-steering DAC provides intrinsically linear outputs to the fine $\Delta \Sigma $ M. The associated delay is mitigated by increasing the coarse sampling rate by a factor of 4. The coarse $\Delta \Sigma $ M significantly relaxes the requirements of the fine $\Delta \Sigma $ M, but despite the faster sampling rate, consumes negligible power, because its noise is canceled for the final output, allowing the use of a relatively large input resistor. The ADC prototype fabricated in a 65-nm CMOS process occupies an area of $0.124~{\text {mm}^{{2}}}$ and consumes only $243~{\mu }$ W from a 1.2-V supply. It achieves 92.0-dB signal-to-noise and distortion ratio (SNDR), 92.3-dB signal-to-noise ratio (SNR), 97.4-dB dynamic range (DR), and 105.7-dB spurious-free DR (SFDR) over a 50-kHz bandwidth without using DAC linearization or calibration. This corresponds to Schreier FoMs of 175.1 dB (SNDR) and 180.5 dB (DR).