FPGA Design and Implementation of Approximate Radix-8 Booth Multiplier

In digital systems, multiplication operations are crucial, particularly in applications like image processing. This paper proposes an approximate radix-8 Booth multiplier designed to enhance performance and reduce complexity compared to traditional counterparts. Specifically tailored for signed-unsigned numbers, the proposed multiplier undergoes evaluation via simulation using Xilinx Vivado software with Artix-7 FPGA Board. Leveraging techniques such as modified Booth encoding and parallel partial product generation, it aims to achieve reduced delay and power consumption. The application of this multiplier is demonstrated through integration into Sobel edge detection. Quantitative metrics, including speedup factor and area reduction, are provided to assess performance improvements over existing systems. Furthermore, the proposed design is highly accurate, detecting 98.87% of edges, demonstrating its practicality and usefulness in digital image processing applications.