ESD/Latch-Up Reliability Enhancements of HV nLDMOSs by Drain-End Horizontally Embedding Different Discrete P+ SCRs

This paper investigates how to balance ESD reliability and latch-up immunity by using TSMC's 0.18-μm high-voltage nLDMOS devices. In order to effectively improve the device's ESD and latch-up immunities, this design adopts the method of horizontally embedding discrete P
⁺
SCR in order to adjust the on-resistance of the device, and increasing the holding voltage will improve the device's latch-up robustness. Due to the low on-resistance and strong discharge current of SCRs, embedding SCRs can effectively enhance the device's ESD discharge current capability. Eventually, the experimental results demonstrate that the design approach of using discrete P
⁺
SCR not only preserves the device's ESD discharge current capability but also effectively mitigates the risk of latch-up occurrence.