Device Simulation Based Machine Learning Technique for III V TFET

Semiconductor devices are becoming increasingly sensitive to even the smallest disruptions resulting from ongoing technological advancements. The minute variations in the nanodevices have become even more discernible as they have been greatly enlarged. Before forward device scaling, it is imperative to resolve these variations thoroughly. TFETs exhibit several drawbacks, including a low on-current that hampers the operational speed, a lifespan of over a decade, ambipolar current behavior, and reduced radio frequency performance. TFETs are very promising solid-state switches for ultralow-power integrated circuits, as they effectively address the issue of power dissipation. The primary obstacles that impede the utilization of TFETs in commercial goods are the requirement for high-quality III-V materials and their derivatives with small physical dimensions, as well as limitations in layout density. This study presents a methodical approach to creating ideal Artificial Neural Network (ANN) models. This involves a thorough consideration of the influence of the ANN size on both model correctness and SPICE simulation. To provide visual representations that are appropriate for circuit simulations, the effectiveness of computer-aided design (CAD) models for innovation is assessed using powerful full-quantum modeling tools to produce visuals.