Comparison of Techniques for Reducing Leakage Current in SRAM: A Study of Gated VDD, MTCMOS, and Clamping Diode Techniques

In the present era, with the reduction of CMOS memory devices to nanoscale dimensions, the reduction of leakage power has emerged as a critical concern in order to achieve efficient power management. SRAM cells provide consistent memory storage throughout data-holding activities, but their smaller size increases their vulnerability to leakage currents. To address this concern, a range of VLSI methodologies, such as Gated-VDD, MTCMOS, and clamping diode approaches, have been used within the HPHS12T SRAM substrate. The Gated-VDD approach is employed to selectively interrupt power supply to inactive blocks or modules, hence mitigating static power efficiency. The MTCMOS technology employs transistors with varying threshold voltages to reduce both static and dynamic power consumption. Nevertheless, these techniques have the potential to cause delays as a result of power-up sequences or heightened circuit complexity. The clamping diode technique minimises leakage current by clamping voltage across a circuit component. The evaluation of the effectiveness of these strategies in lowering leakage power, enhancing write static noise margin (WSNM), and minimising delays was conducted by applying them in Cadence Virtuoso 45nm technology. A comparative analysis was conducted to evaluate the efficiency of various low-power techniques, including HPHS12T, gated VDD, MTCMOS, and clamping diode, in the context of HPHS12T cells.