Study on Enhancing ESD Reliability Through A Area Modulation of High-Voltage nLDMOSs with the Drain Embedded STI

A TSMC's
$0.18-\mu \mathrm{m}$
BCD process for high-voltage LDMOS devices is utilized in this paper. To effectively disperse the high temperatures generated during device operation and prevent ESD in circuit devices, a Shallow Trench Isolation (STI) layer has been embedded at the drain end of the nLDMOS. By the employing STI to isolate the N
⁺
area at the center of the drain end, the study explores the reliability of STIs at various proportions of the drain end area concerning ESD capability. As the current passes through the drain end, the temperature rises, and there is a greater increase in I
t2
when there is a larger temperature difference between the central N
⁺
and the outer N
⁺
. From the experiment data, when the STI area reached 40% of the drain end, I
t2
could increase to 1.97A, exhibiting the best quality factor of
$2309.357\ \mu \mathrm{A}/\mu \mathrm{m}2$
.