Oriented IC Design Approach for Small-Volume, Performance-Demanded Edge-AI ASICs

The first-tier CMOS process for the design of integrated circuits (ICs) is often unavailable for small-volume edge-artificial intelligence (AI) application-specific integrated circuits (ASICs), highlighting demanded design goals in either speed, power, or leakage. The urgency in entering the market may force the designer to consider using the second-tier process with iterative designs to meet the demanded design goals. The overall paid prices are a long time to market, a long time to production, and a high development cost. This work proposes an oriented IC design approach for edge-AI ASICs to quickly meet uniquely demanded design goals and achieve a short time to market and production with low cost. We implement a test chip in 22nm CMOS for concept proving, where a deep neural network accelerator for dysarthria speech conversion is the vehicle to illustrate the proposed design approach in increasing the speed with a lower area cost and power consumption.