A D-Band Power Amplifier in 40-nm CMOS Process for Next-Generation Communication System

This paper proposes a two-way D-band power amplifier that utilizes a simple Y-shape junction power distributor and combiner to achieve required output power and gain. The fabricated chip adopted the 40-nm Bulk CMOS process technology. For each way of the power amplifier, the circuit architecture was designed as cascading three-stage amplifiers of common-source configuration. The measured s-parameters show a peak small-signal power gain of 10.65 dB at 130 GHz with a 19.5-GHz 3-dB bandwidth from 126 to 145.5 GHz. The measured maximum output power, output 1-dB compress point, and maximum power added efficiency are 6.31 dBm, 2.03 dBm, and 4.76%, respectively, at 144 GHz. The chip size with all pads is
$0.673 \times 0.542\ \text{mm}^{2}$
and the total dc power consumption is 57 mW.