Tunnel FET: Principles and Operations

Summary

Recently, the performance and density of integrated circuits (ICs) have been considerably increased to meet the growing requirements of electronic devices for computing, smartphones, communication, and other applications with continual improvements in speed, cost, and power consumption. These achievements can be obtained through the process of scaling the dimensions of the metal–oxide–semiconductor field‐effect transistor (MOSFET) as the building block of ICs, following Moore's law. However, MOSFET scaling in the nanoscale regime is approaching the fundamental physical limits. Based on the Boltzmann limit, a conventional MOSFET in today's ICs requires at least 60 mV of gate voltage to increase the current by 1 order of magnitude at room temperature. Tunnel field‐effect transistor (TFET) has been introduced as a potential candidate for the conventional MOSFET. In principle, a conventional TFET is a gated p‐i‐n reverse‐biased diode, in which carriers' tunnel from source to channel through the process of band‐to‐band tunneling (BTBT). This device can be considered as an efficient electronic switch with a subthreshold swing of less than 60 mV/dec. The focus of this chapter is to optimize the electrical characteristics of a TFET device by simultaneously achieving the lowest possible off‐state current, the lowest average subthreshold swing over a wide range of drain currents, and the highest possible on‐state tunneling current. Basically, to increase the BTBT current and to achieve a step‐like behavior from off‐state to on‐state, the transmission probability of the tunneling barrier should approach one for a small variation in the gate voltage around the threshold voltage value. This requires a strong modulation of the energy bands by the gate bias as well as a very thin tunneling barrier. There are different techniques to improve TFET performance, including doping engineering, material engineering as well as geometry and structure engineering, which will be comprehensively discussed. The discussions in this chapter will provide a comprehensive understanding of TFET devices, which can pave the way for designing energy‐efficient high‐speed nanoelectronic circuits.