Effective Suppression of Vt Roll-Up for pMOS With Embedded SiGe Source/Drain

The anomalous roll-up of the absolute value of threshold voltage (
$\vert {V}_{\text {t}}\vert $
) is observed for pMOS with embedded SiGe source/drain (eSiGe S/D) as the gate width decreases. It is revealed that the raised eSiGe height reduction for the wide pMOS may result in more B atoms diffusion into channel region from Si cap layer, causing the net doping level decrease of channel region as well as
$\vert {V}_{\text {t}}\vert $
. The wider the pMOS, the smaller the
$\vert {V}_{\text {t}}\vert $
is; ~60%
$\vert {V}_{\text {t}}\vert $
increase can be observed as the gate width decreases. It is demonstrated that increasing the raised eSiGe height together with reducing B concentration in Si cap layer can effectively realize 20%
$\vert {V}_{\text {t}}\vert $
decrease without the pMOS performance degradation.