Deductive Formal Verification of Synthesizable, Transaction-Level Hardware Designs Using Coq

We present the compilation process of synthesizable, transaction-level hardware designs into Gallina code. This allows the Coq theorem prover to execute formal verification scripts on top of the automatically generated code to prove individual theorems. The novelty of this work is the use of PDVL (Programming Design and Verification Language), which adds specific language constructs to System Verilog to enable an aspect-oriented, transaction-level design style. In this paper, we show that PDVL code can also be compiled into Gallina code, with the advantage that it is highly usable for theorem proving and perfect for using the Coq proof assistant. We outline individual proof strategies for theorem proving, sequential equivalence checking, property checking, and show applications of symbolic simulation techniques. This is done by using a complex timer peripheral, AES and UART modules as well as RISC-V based designs.