TSA-TICER: A Two-Stage TICER Acceleration Framework for Model Order Reduction

To enhance the post-simulation efficiency of large-scale integrated circuits, various model order reduction (MOR) methods have been proposed. Among these, TICER (Time-Constant Equilibration Reduction) is a widely-used resistor-capacitor (RC) network reduction algorithm. However, the time constant computation for eliminated-node classification in TICER is quite time-consuming. In this work, a two-stage TICER acceleration framework (TSA-TICER) is proposed. First, an improved graph attention network (named BCTu-GAT) equipped with betweenness centrality metric (BCM) based sample selection strategy and bi-level aggregation-based topology updating scheme (BiTu) is proposed to quickly and accurately determine all the eliminated nodes one time in the TICER. Second, an adaptive merging strategy for the new fill-in capacitors are designed to further accelerate the insertion stage. The proposed TSA - TI CER is tested on RC networks with the size from 2k to 2 million nodes. Experimental results show that the proposed TSA-TICER achieves up to 796.21X order reduction speedup and 10.46X fill-in speedup compared to the TICER with 0.574% maximum relative error.