Branch-Aware Self-Test Program Generation for Processor Cores

Software-based self-testing is a promising solution to post-deployment testing for processor cores embedded in long-life mission-critical systems. One popular approach to self-test program generation is to convert each scan-based test pattern to an instruction sequence that, when executed, implicitly applies the test pattern. However, this approach suffers low conversion quality for branch instructions. In this paper, we develop a branch-aware test program generator to improve the conversion efficiency for branch instructions. The test program generator considers the actual and predicted branch conditions to derive the instruction addresses that guarantee the desired program execution order. Furthermore, we optimize the test program template and recycle the wasted program blocks to reduce the test program footprint. The proposed test program generator is applied to a five-stage RISC-V processor with branch prediction. The generated test program achieves 90.68% transition delay fault coverage and reduces the test program size by 76%.