3D Architecture to Integrate Backside Power Interconnect and Integrated Passive Device for Thermal and Electrical Performance Management of Logic Chip

A novel 3D architecture with backside power delivery network (BSPDN) and embedded 3D high density Si capacitor is proposed with the superior electrical performance and heat dissipation. Typical backside power-via technology with carrier is found to have the thermal dissipation issue. The good concentration of the mimic BSPDN daisy chain (2K contact TSVs) describes the proposed structure is well- connected after carrier with 3D high density Si capacitor and TSV integration by wafer on wafer bonding. The 3D high density (>40% density within chip) Si capacitor which is targeting to implement into carrier has good capacitance (>1.0 μF/mm2) and small capacitance variation (<8%) under the applied voltage in the range of −2 to 2 V. Moreover, the proposed structure could reduce the temperature around 26% as compared with a typical one from thermal viewpoint. In addition, from the package-level viewpoint, the proposed structure also could reduce the temperature as high as 43%.