Pattern Generation for Efficient Acceptability Verification of Approximate Circuits

Approximate computing allows designers to trade-off precision with hardware cost and power consumption. The possible degree of approximation relies on a realistic quality assessment with functional input sequences and metrics to quantify the error magnitude. The complete exploration of the input space is impracticable in most cases but a partial input sequence might underestimate the severity of possible errors. The paper at hand presents an approach to generate patterns for efficient acceptability verification of an approximate circuit and to complement conventional quality assessment methods. A modified miter design indicates the differences between the approximate and the precise circuit, and an existing ATPG flow is used to maximize the differences. A case study on JPEG2000 decoder validates that our approach can efficiently and effectively identify unacceptable approximate results where conventional image quality assessment methods failed.