12LP FinFET CMOS Ultra-Low Leakage SRAM Devices with 0.54pA/cell Istby

Low power device with ultra-low leakage (ULL) is the mainstream for current and future nano Complementary Metal-Oxide-Semiconductor (CMOS) memory devices. In addition, leakage power reduction during data-retention mode in Static random-access memory (SRAM) standby needs to be significantly improved with reduced supply voltage. In this paper, ULL SRAM designed on GlobalFoundries 12LP CMOS technology is presented. Achieving a record low device level retention standby leakage of 0.54pA/cell, together with −20% Vtsat mismatch reduction and +10%/+12% n/pSRAM performance boost. In addition, cross wafer uniformity of SRAM standby leakage has been reviewed with −35% within-wafer (WiW) improvement.