BEOL Dielectric Film Delamination Reliability Improvement by Eliminating Silicon-Rich Interface

Fluorinated silica glass (FSG) has been widely used as an intermetal dielectric (IMD) due to its low dielectric constant (low k) and is normally deposited by a two-step process. This process consists of a high-density plasma (HDP) FSG layer for gap-fill, followed by a plasma enhanced chemical vapor deposition (PECVD) FSG layer for planarization and as an IMD. The interface between these two films plays an important role in film property and stability. A silicon-rich layer at the interface of the two layers can cause an adhesion issue which can lead to film delamination during subsequent thermal cycles. This is a serious reliability problem for the wafer fabrication process. This paper focuses on the effect of the silane (SiH4) gas flow rate when switching from HDP to PECVD and its effect on the interface layer properties. Experiments were carried out with multiple recipe conditions of varying delays in switching the silane gas flow. Inline measurement of goodness of fit (GOF) and failure analysis (FA) data were collected for analysis. A shorter delay for the silane gas flow ramp during recipe switching formed a silicon-rich layer at the interface, which causes delamination. A perfect SiO2 interface with no silicon-rich layer is observed for a delay of 5sec or more, which is desirable for good film properties and wafer quality. This finding can be applied to improve adhesion and reliability on other processes such as IMD liner or STI HDP liner where a non-homogeneous film stack is formed by switching silane gas flow rate.