Implementation of a PnR Flow at Block Level to Achieve the High Utilisation Rate

This research work presents the implementation of a sophisticated Place and Route (PnR) flow specifically tailored for block-level design in VLSI circuits. The primary focus is optimizing silicon area utilization and improving overall design efficiency. The proposed flow encompasses strategic floorplanning, efficient placement of standard cells and macros, advanced clock tree synthesis, and sophisticated routing techniques. Special attention is given to the integration of logic restructuring during the PnR process to further enhance area utilization while addressing routing challenges. The methodology is designed to accommodate a 40nm technology node, featuring 34 macros, 38k standard cells, a 1GHz clock frequency, and a 1.1V supply voltage. Through the utilization of state-of-the-art algorithms and tools, the study aims to achieve high silicon area utilization, meeting or exceeding design constraints such as a 5% maximum IR drop and a power budget of 600mW. The outcomes are assessed based on achieved utilization rates, performance metrics, and adherence to design specifications. The results of this study showcase the advantages of the proposed PnR flow, demonstrating a notable increase in silicon area utilization. By achieving a high utilization rate, the design not only maximizes the efficiency of the available space but also aligns with the demands of contemporary semiconductor technology.