Design of Low Power High-Speed LMS Adaptive Filter For Biomedical Applications

The COVID-19 pandemic continues to impact communities worldwide. Patients suffered from COVID-19 are at increased risk of a broad range of cardiovascular disorders. An electrocardiogram (ECG) is a simple test which graphically represents the heart’s rhythm and the electrical activity of the heart during a cardiac cycle. Therefore, precise detection of electrocardiogram signals is the elementary step in clinical diagnostics. This research paper presents an implementation of an adaptive Least Mean Squared (LMS) digital filter for trustworthy ECG signal detection. The work aims at Multiple Constant Multiplication (MCM) operations and Common Sub-expression Elimination (CSE) techniques to improve precision and reduce power consumption. The filter is modeled using Verilog hardware descriptive language and implemented on Xilinx ML605 FPGA (XC6VLX240T1FFG1156 FPGA) Embedded Development Kit. Comparison with the direct implementation of LMS filter DFG shows that the number of employed FPGA LUTs is reduced by 65.53%, power consumption is reduced by 55.98%, frequency of operation of the device is increased by 52.88%, and the throughput is increased by 159.14%. The results show reduced power consumption and corrected accuracy, suggesting that the proposed method is capable of accurately detecting ECG signals.