Synchronization Support in 64-bit Out-Of-Order Superscalar Dual-Core RISC-V Processor

This paper discusses the implementation of atomic instructions in a dual-core 64-bit out-of-order superscalar processors based on the open-source RISC-V instruction set architecture. Leveraging the advantage of RISC-V’s modularization characteristics, each core implements RV64IMAFDC extension and optional supervisor and user mode privilege levels. In this paper, we focus on the A-extension, the atomic instruction set extension. This extension introduces instructions that provide atomic memory operations, enabling synchronization across multiple RISC-V harts within the same memory space. Our goal is to present an efficient execution flow of atomic memory operation instructions and Load-Reserved/Store-Conditional instructions for a dual-core System-on-Chip. We subsequently verify the synchronization capabilities through the execution of a standalone game application on SoC implemented on a Xilinx Kintex UltraScale KU085 FPGA-based board.