Hybrid Hardening Approach for a Fault-Tolerant RISC-V System-On-Chip

The New Space era has driven a wide array of applications in novel space missions with an increasing demand for processors with high computational capabilities while simultaneously maintaining low power consumption, flexibility, and reliability. Soft-core processors based on commercial off-the-shelf (COTS) technologies have emerged as a viable alternative that can meet these requirements but need to be hardened to operate in harsh environments. In this work, we propose and apply fault tolerance strategies based on software recovery using checkpoint and rollback operations to extend the capabilities of a hardened soft-core RISC-V-based system-on-chip. The proposed strategy relies on the fault awareness provided by the system-on-chip hardening to trigger the software recovery without the addition of dedicated structures or processor cores. Notably, we investigate the effectiveness of this multilayer hardening strategy, which combines software recoverability and hardware redundancy. For that, a neutron irradiation campaign was performed. The results show the effectiveness of the proposed approach, achieving 45.09% of effective software recovery operations with low overhead for performance and resource utilization.