Learnings from Electrical and Functional Interoperability Validation of a pcie Gen4 16Gbps High-Speed Serial Link in Server Platforms

Robust electrical link as measured by eye opening (eye width and eye height) at the receiver of a high-speed serial link is important. Equally important is the repeatable functional interoperability as measured by successful training to various link states by the link partners on either side of the channel. This paper presents learnings from such post-silicon validation of a Peripheral Component Interconnect Express (PCIe) physical layer implemented in a 10nm FinFET CMOS process supporting PCIe Gen4 (16Gbps data rate) with backwards compatibility to PCIe Gen1/2/3 data rates of 2.5, 5.0 and 8.0 Gbps. The paper also discusses, presented as case studies, the debug techniques used to test, root cause, and resolve interoperability issues when linked with various link partners supporting PCIe technology.