An Efficient Hardware Design of CoAP Protocol for The Internet of Things

CoAP (Constrained Application Protocol) plays a crucial role in IoT by providing a lightweight and efficient communication protocol tailored for resource-constrained devices, facilitating seamless and reliable data exchange. This paper proposes a novel hardware accelerator for CoAP to address critical performance challenges in the context of the Internet of Things (IoT). The proposed method focuses on optimizing two key parameters, namely latency and execution time, through a carefully designed hardware setup. Implemented using VHDL on Xilinx Virtex-7 FPGA, the study demonstrates through extensive evaluations that the proposed method outperforms traditional software-based CoAP implementations. It achieves reduced execution times and lower latency across varying payloads and sampling rates, with a power consumption of 4.63 mW. These results signify a notable improvement in CoAP functionality, positioning the proposed hardware acceleration approach as a promising candidate for enhancing communication protocols in IoT environments.