Physical Modeling of Perimeter-Gated SPADs in Standard Deep Submicron CMOS Processes

In this paper, we present a new TCAD device simulator developed for comprehensive physical modeling for perimeter-gated single photon avalanche diodes (SPADs) implemented in standard deep submicron CMOS processes. The perimeter-gated SPAD is an improved version of the SPAD with an additional gate terminal to help prevent perimeter edge breakdown as well as improve performance. The model includes all the features of a real SPAD device with an added gate terminal implemented in a standard CMOS deep submicron process including shallow trench isolation (STI). Using the developed model, the underlying physics of perimeter-gated SPAD devices including electric field distribution, total current density, electrostatic potential, and conduction band energy has been examined with the impact of the extra gate terminal.