Investigating the Effect of Hyper-Parameter Settings on Simulated Annealing-Based High-Level Synthesis Design Space Exploration

In the increasingly complex landscape of Very-Large-Scale Integration (VLSI) design, the incorporation of High-Level Synthesis (HLS) has become a transformative paradigm due to its numerous advantages. One of them is its ability to generate hardware circuits with different area vs. performance trade-offs from the same behavioral description. This is typically achieved by setting synthesis directives, such as pragmas, to control the synthesis of arrays and loops. Among all the different pragma combinations, the most important ones are those leading to Pareto-optimal hardware circuits. Due to the multi-objective nature of this problem and the large number of pragma combinations, exhaustive enumeration of all possible combinations is normally not possible, necessitating heuristics that lead to good results quickly. Simulated Annealing (SA) is one such heuristic well-known for producing good results in this type of multi-objective optimization problem. The main problem with SA is its high dependency on hyper-parameters. This paper investigates the use of SA for HLS design space exploration (DSE) and examines the effect of different hyper-parameters on the quality of exploration results versus the runtime of the exploration process. Experimental validations on diverse benchmarks demonstrate the effectiveness of the approach in achieving a balance among critical metrics such as area, latency, and runtime.