Practical Considerations on ESD Testing

Testing and simulation are critical to accurate onchip electrostatic discharge (ESD) protection designs, particularly for complex ICs in advanced technologies. This paper discusses two important considerations in practical on-chip ESD protection designs. First, accurate ESD design simulation relies on ESD testing for calibration where the input ESD stimulus plays a key role in precisely correlating ESD simulation with ESD testing, e.g., using human body model (HBM) ESD zapping and transmission-line pulse (TLP) measurement. Second, very-fast TLP (VFTLP) testing is widely used for charged device model (CDM) ESD characterization, which is questionable because transitional pad-based CDM ESD protection method may be fundamentally wrong. Understanding these two ESD testing factors are critical to ESD design optimization and prediction, as well as ESD protection validation.