Customizing ATPG User-Defined Stresses and Tests To Target Cell-Neighborhood-Bridging Defects

Cell-neighbor-bridging defects between logic and filler cells were detected on an automotive design after a highly resistive short defect was activated during an internal reliability assessment, having previously passed all wafer probe and package Final Test stresses and screens. The impacted cell’s nodes were confirmed to be stressed and tested as intended at the wafer probe insertion, but not sufficiently enough to activate and observe the effect of the highly resistive defect’s impact on the circuit behavior. The paper discusses a new methodology that identified and located all instantiations of the affected cell combinations in the sea of gates, and development of new stress and test stimuli using User Define Fault Models (UDFM) to target only the affected cell combinations. Limiting the reach of the enhanced stress and test in this way enabled a cost effective and high-quality solution to accelerate activation and improve detectability of the latent defect during silicon test flows.