Scenario-based Test Content Optimization: Scan Test vs. System-Level Test

Test application to state-of-the-art integrated circuits usually consists of multiple test insertions: wafer sort, final test and system-level test (SLT). This paper considers optimization of test content, taking requirements of specific scenarios, such as expected yield levels, test costs and criticality of test escapes, into account. An integrated cost model is proposed and applied to four different test setups on a medium-complexity RISC-V microprocessor. Our results indicate opportunities for up to ~ 40% total cost reduction compared to today’s industrial practice. They also provide insights on the relative importance of various cost contributors, such as the number of available scan test insertions or the specific SLT workload used.