Multi-Level Reference for Test Coverage Enhancement of Resistive-Based NVM

As technology scales down, the interconnect parasitic resistance more dominantly affects performance degradation and test escapes. The wire resistance increase is especially a great challenge in resistive-based non-volatile memories (NVM) such as magnetic random access memory (MRAM) and resistive RAM (ReRAM) because it can cause faulty reading of the data. The resistive-based NVMs perform the read operation by sensing the bitcell resistance relative to a reference value. Therefore, additive parasitic resistances along the read path, including the bitline (BL) and sourceline (SL) resistances, may cause incorrect read operation. The additive path resistance also makes defect screening harder. A defect screening method designed to detect faulty bitcells located near the sensing circuit may not effectively screen out a bitcell located far from the sensing circuit with the same defectivity level and lead to test escapes. Utilizing a multi-level reference, the proposed new testing scheme compensates for the additive line resistance effect and improves coverage for local defect screening. The detected fault will be further evaluated for correction by ECC or repaired to maximize field coverage. The proposed method is applicable to existing industrial memory built-in self-test (MBIST) solutions with minor modifications.