Comparative Evaluation of 6T, 8T and 10T Ternary SRAM Cells Schemes for Future VLSI and Power Electronics

A ternary SRAM cell can be built as a restorage element by joining ternary inverters back-to-back. In this work, it is shown that the evaluation of ternary logic using the 8 T SRAM cell is superior than that using the 10T SRAM cell. SRAM cells with 10T and 8 T capacities are used to test the many designs. With its tiny space and power efficiency, the 8 T ternary SRAM cell is becoming a top contender for next-generation on-chip memories as VLSI technology keeps becoming smaller. The 8T architecture allows for the dependable storing of three logic states per cell due to the extra transistors compared to a regular 6T SRAM cell. With ternary storage, one can keep noise margins the same while increasing memory density. Ternary 8T SRAM is an ideal candidate for more research and optimization as a small, energy-efficient memory subsystem because to its dependable performance and simple control logic.